1. Field of the Invention
The present invention relates to multi-lane serial data links
2. Description of Related Art
Binary signaling is a popular signaling scheme widely used in serial data link; for instance, HDMI (High Definition Multi-media interface). In a serial data link, a bit stream is transmitted from a transmitter to a receiver via a communication channel (e.g. a cable) at a certain symbol rate fs in accordance with a timing of a clock of the transmitter; each symbol within the bit stream represents either a logical “1” or a logical “0” datum (hereafter, “1” and “0”); a “1” is represented by a voltage of a first level of a symbol duration Ts, where Ts=1/fs, while a “0” is represented by a voltage of a second level of the symbol duration Ts; and as a result, the bit stream is represented by a voltage signal toggling back and forth between the first level and the second level in accordance with the bit stream transmitted. Some serial data links, e.g. HDMI, utilize multiple lanes of communication channels for transmitting multiple bit streams concurrently for a greater throughput.
A functional block diagram of a receiver 100 of a single-lane serial data link is depicted in FIG. 1. Receiver 100 comprises an equalizer 110 for receiving a received signal and outputting an equalized signal, and a CDR (clock-data recovery) circuit 120 for receiving the equalized signal and outputting a recovered clock and a recovered bit stream. CDR circuit 120 comprises a BPD (binary phase detector) 121 for receiving the equalized signal and the recovered clock and outputting the recovered bit stream and a phase error signal, a CDR filter 122 for receiving the phase error signal and outputting a clock control signal, and a clock generation circuit 123 for receiving the clock control signal and outputting the recovered clock.
An exemplary timing diagram of receiver 100 is shown in FIG. 2. As shown in FIG. 2, the received signal is dispersed due to dispersion caused by the communication channel and therefore the binary nature of the signal is obscured. Equalizer 110 of FIG. 1 is used to equalize the received signal, so that the dispersion is corrected and the resultant equalized signal has two distinct levels representing the bit stream transmitted by the transmitter. CDR circuit 120 of FIG. 1 is used to properly establish a timing of the recovered clock, so that a rising edge of the recovered clock is aligned with a center of a datum bit of the bit stream (see 201, 202, 203, 204, 205, 206, 207, 208) and a falling edge of the recovered clock is aligned with a transition of the bit stream (see 211, 212, 213, 214). The recovered bit stream is conveniently generated by sampling the equalized signal using the rising edge of the recovered clock. In the meantime, an edge sample obtained by sampling the equalized signal using the falling edge of the recovered clock is used to generate the phase error signal. Ideally, a falling edge of the recovered clock is aligned with a bit transition of the bit stream and therefore the resultant edge sample should have no statistical correlation with the bit stream. If the edge sample sides with the recovered bit prior to the transition, it suggests a timing of the recovered clock is too early; if the edge sample sides with the recovered bit following the transition, it suggests the timing of the recovered clock is too late. In this manner, the phase error signal is generated by BPD 121 and serves to adjust the timing of the recovered clock. The phase error signal is filtered by CDR filter 122, resulting in the clock control signal. The clock generation circuit 123 generates the recovered clock in accordance with the clock control signal. The recovered clock is thus controlled in a closed loop manner so as to align with the timing of the equalized signal.
Receiver 100 of FIG. 1 is useful for a single-lane serial data link. For a multi-lane serial data link comprising, for instance, four lanes, four of such receivers are needed, one for each of the four lanes. In this case, one can simply use four copies of the receiver 100 for FIG. 1.
There are generally two schemes for embodying CDR circuit 120 of FIG. 1: one is an analog scheme, and the other is a digital scheme. In the analog scheme, the intermediate signals involved are analog in nature: the phase error signal is usually a current-mode signal; the CDR filter 122 is usually a load circuit comprising a serial connection of a resistor and a capacitor; the clock control signal is usually a voltage signal; and the clock generation circuit 123 is usually a VCO (voltage-controlled oscillator). In the digital scheme, the intermediate signals involved are digital in nature: the phase error signal is usually a ternary digital signal; the CDR filter 122 is a digital filter usually comprising two multipliers, one accumulator, and one adder; the clock control signal is usually a phase selection code specifying a clock phase to be selected; and the clock generation circuit 123 usually comprises a phase selection circuit that selects a clock phase among a plurality of clock phases of a multi-phase clock in accordance with the phase selection code. The digital scheme is attractive due to its digital nature, lending itself to ease of design using design automation tools (i.e., logic synthesis and automatic place and route). Besides, compared to the analog scheme, the performance of the digital scheme is more consistent, more predictable, and less sensitive to noise and variation of supply voltage and temperature. Unfortunately, for high-speed serial links of interest (such as HDMI), the symbol rate is too high for the CDR circuit to operate at the same clock rate (as the symbol rate of the serial link). For this reason, people are forced to resort to block processing, where the phase error signal is buffered and then processed as a block; this allows the CDR circuit to operate at a lower clock rate than the symbol rate of the serial link. For instance, if the block size is ten, then the phase error signal is buffered and processed, ten samples at a time, at a ten-time slower rate than the symbol rate. The drawback, however, is that this introduces a latency in the CDR circuit and degrades the performance of the clock recovery. Therefore, the analog scheme usually has a higher ceiling in performance for clock recovery. However, the digital scheme is more amenable to the process migration of modern CMOS (complementary metal oxide semiconductor) technologies, and can effectively take advantage of the ever increasing circuit speeds and shrinking circuit sizes. The analog scheme, on the other hand, is not as amenable to the process migration, and thus is generally not as power and size efficient as the digital scheme.